Ph.D.: PhD (Engg.), Jadavpur University (2019)

Post Graduate: M.Tech. in VLSI Design and Microelectronics Technology, Jadavpur University (2013)

Under Graduate: B. Tech in Electronics and Communication Engineering, West Bengal University of Technology

Assistant Professor in the Department of Electronics and Communication Engineering, Netaji Subhash Engineering College since July 2016 till date Senior Research Fellow in the Department of Electronics and Telecommunication Engineering, Jadavpur University [ December 2013- June 2016]. Senior Research Fellow in the Department of Electronics and Telecommunication Engineering, Jadavpur University [August 2012- December 2013].

Senior Member, IEEE

M.Tech. (Gold Medalist)

Advisor of IEEE Electron Devices Society Student Branch Chapter, NSEC. Former Treasurer, , IEEE Electron Devices Society Kolkata Chapter. Invited talks and tutorials co-chair at IEEE International Conference for Convergence in Engineering from 5th to 6th September 2020 organized by Netaji Subhash Engineering College, Kolkata. Organizing Co-Chair at 2nd IEEE International Conference VLSI Devices Circuits and Systems (VLSI DCS 2020) from 21st to 22nd March 2020 organized by IEEE EDS Student Branch Chapter of Meghnad Saha Institute of Technology, Kolkata.

Modeling and simulation of low power nano devices, Analog VLSI Circuit designing,

Journal of Physics D: Applied Physics, IOP., Silicon, Springer, Journal of Computational Electronics, Springer, International Journal of High Speed Electronics and Systems (IJHSES), Computers and Electrical Engineering, Elsevier.

Modeling and simulation of low power nano devices, Analog VLSI Circuit designing, Statistical Analysis using ML

Undergraduate: • Electronic Devices • Analog Electronic circuits • Digital Systems Design • Digital Signal Processing • CMOS VLSI Design • Control System and Instrumentation • Neural Network and Fuzzy Logic Control

Co-convener, Departmental Academic Committee (DAC) Member, Departmental Library Committee Member, Departmental News Magazine Committee Member, Departmental Students Affairs Committee Member, Departmental Research Committee Organizing Committee member of ICCE Conference at NSEC , 2020

1. ML based statistical analysis of the impact of process parameter variations on the frequency of Low Power VCO

Mentor of present 4th year [2020-2024] batch

1. Rittik Ghosh, Saheli Sarkhel and Priyanka Saha, " Design and analysis of Z shaped InGa0.5As0.5/Si tunnel FET using non-equilibrium Green’s function model for hydrogen gas sensing application", Micro and Nanostructures, Elsevier, In press, July 2023 (SCI, IF:3.22). 2. Koyel Mukherjee, Trisha Sau, Sneha Upadhyay, Susmita Mitra, Arpita Bhowmik, Saheli Sarkhel, Soumya Pandit, Rajat Kumar Pal, "A 588?nW, 1 nA current reference circuit with extremely low (0.002%/V) line sensitivity over a wide supply voltage range and low temperature coefficient", Int. Journal of Numerical Model., Wiley, Vol. 35, Issue 4, 2022. (SCI, IF: 1.6). 3. Toushik Santra, Ankit Dixit, Rajeewa Kumar Jaisawal, Sunil Rathore, Saheli Sarkhel and Navjeet Bagga, "Investigation of geometrical impact on a P+ buried negative capacitance SOI FET", Microelectronics Journal, Elsevier, Volume 130, 2022. (SCIE, IF: 2.2) 4. Priyanka Saha , Saheli Sarkhel and Subir Kumar Sarkar "Two-Dimensional Potential and Threshold Voltage Modeling of Work Function Engineered Double Gate High-k Gate Stack Schottky Barrier MOSFET", Journal of Electronic Materials, Springer, Vol.8, Issue 6, pp-3823-3832, March 2019 (SCI, IF:2.1). 5. Saheli Sarkhel, Priyanka Saha and Subir Kumar Sarkar, “Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel”, Silicon, Springer publications, Volume 11, Issue 3, pp 1421–1428, June 2019. (SCIE, IF- 3.4). 6. Priyanka Saha, Saheli Sarkhel and Subir Kumar Sarkar ,“3D Modeling and Performance Analysis of Dual Material Tri Gate Tunnel Field Effect Transistor”, in IETE Technical Review, Taylor and Francis, Vol.36 Issue 2, pp-1-13,March 2018 (SCIE, IF – 2.4). 7. Priyanka Saha, Saheli Sarkhel and Subir Kumar Sarkar , "Compact 2D threshold voltage modeling and performance analysis of ternary metal alloy work-function-engineered double-gate MOSFET", in Journal of Computational Electronics, Springer, Vol.16.No.3,pp-648-657, June 2017 (SCIE , IF: 2.1). 8. Ranita Saha, Saheli Sarkhel and Subir Kumar Sarkar, "Analytical Modeling and performance characterization of a Double Gate MOSFET with Dielectric Pockets incorporating workfunction engineered binary metal alloy gate electrode for subdued SCEs", in IETE Technical Review, Taylor and Francis, Vol. 35, Issue 5, pp-506-513, 2017 (SCIE, IF – 2.4) 9. Saheli Sarkhel, Navjeet Bagga and Subir Kumar Sarkar, " A compact analytical model of binary metal alloy silicon-on-nothing (BMASON) tunnel FET with interface trapped charges" in Journal of Computational Electronics, Springer, September 2017, Volume 16, Issue 3, pp 704–713 (SCIE , IF: 2.1) 10. Navjeet Bagga, Saheli Sarkhel and Subir Kumar Sarkar. “Exploring the asymmetric characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for enhanced performance.” In IETE Journal of Research, Taylor and Francis, Volume 62, 2016 - Issue 6, Pages 786-794 , 2016 (SCIE, IF – 1.5). 11. Saheli Sarkhel, Navjeet Bagga and Subir Kumar Sarkar. “Compact 2D Modeling and Drain Current Performance Analysis of a Work Function Engineered Double Gate Tunnel Field Effect Transistor.” In Journal of Computational Electronics, Springer, Vol. 15, Issue 1, pp. 104-114, March 2016 (SCIE , IF: 2.1). 12. Saheli Sarkhel and Subir Kumar Sarkar. “A compact quasi 3D threshold voltage modeling and performance analysis of a novel linearly graded binary metal alloy quadruple gate MOSFET for subdued short channel effects.” In Superlattices and Microstructures, Elsevier, Vol. 82, pp. 293-302, 2015 (SCI, IF – 3.22). 13. Saheli Sarkhel and Subir Kumar Sarkar. “A comprehensive two dimensional analytical study of a Nanoscale Linearly Graded Binary Metal Alloy Gate Cylindrical Junctionless MOSFET for improved short channel performance.” In Journal of Computational Electronics, Springer, Vol.13, pp. 925-932, 2014 (SCIE , IF: 2.1). 14. Saheli Sarkhel, Bibhas Manna and Subir Kumar Sarkar. “Threshold voltage modeling and performance comparison of a novel linearly graded binary metal alloy gate junctionless double gate metal oxide semiconductor field effect transistor.” In Indian Journal of Physics, Springer, Vol. 89, No.6, pp. 593–598, 2015 (SCIE, IF – 2.0). 15. Saheli Sarkhel, Bibhas Manna and Subir Kumar Sarkar. “A Compact Two Dimensional Analytical Modeling of Nanoscale Fully Depleted Dual Material Gate strained SOI/SON MOSFETs for subdued SCEs.” In Journal of Low Power Electronics, ASP, Volume 10, Number 3, pp. 383-391, September 2014. (ESCI, Scopus Indexed, IF-0.84) 16. Saheli Sarkhel, Bibhas Manna and Subir Kumar Sarkar. “Analytical Modeling and Simulation of a Linearly Graded Binary Metal Alloy Gate Nanoscale Cylindrical MOSFET for reduced short channel effects” In Journal of Computational Electronics, Springer, Vol. 13, No. 3, pp. 599-605, April, 2014. (SCIE , IF: 2.1) 17. Saheli Sarkhel, Bibhas Manna, P.K. Dutta and Subir Kumar Sarkar. “Analytical Model for performance comparison of a nano scale Dual Material Double Gate Silicon on Insulator (SOI) and Silicon on Nothing (SON) MOSFET.” In Journal of Nano Engineering and Nano Manufacturing, ASP, Vol.4, No. 3, pp. 182-188, 2014. 18. Bibhas Manna, Saheli Sarkhel, Ankush Ghosh, S. S. Singh and Subir Kumar Sarkar. “Dual Material Gate Nanoscale SON MOSFET: For Better Performance.” In International Journal of Computer Application (IJCA), ISBN: 973-93-80875-27-15, 2013. 19. Bibhas Manna, Saheli Sarkhel, N. Islam, S. Sarkar and Subir Kumar Sarkar. “Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application.” In IEEE Transaction on Electron Devices, Vol-59, Issue-12, pp. 3280-3287, 2012. (SCI, IF – 3.1) 20. Saheli Sarkhel, Sounak Naha and Subir Kumar Sarkar “Reduced SCEs in Fully Depleted Dual-Material Double-Gate (DMDG) SON MOSFET: Analytical Modeling and Simulation.” In International Journal of Scientific and Engineering Research, Volume 3, Issue 6, June 2012 Edition.

1. Ilika Mitra, Wasim Habib, Silpi Sarkar, Saheli Sarkhel and Soumya Pandit, “An approach for modeling propagation delay of a subthreshold inverter incorporating DIBL effect”, 5th International Conference “2023 Devices for Integrated Circuit (DevIC)”, at Kalyani Government Engineering College from 7-8 April, 2023, organized by IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC and with technical partnership from IETE Kolkata Chapter and IEEE EDS Kolkata Chapter. 2. Saheli Sarkhel, Sunil Rathore, Priyanka Saha, Ankit Dixit, Taha Saquib, Rajeewa K. Jaiswal, P.N. Kondekar and Navjeet Bagga, “Analytical Model of Dual Cavity Nanowire Tunnel FET-based Dielectric Modulated Biosensor”, 5th International Conference “2023 Devices for Integrated Circuit (DevIC)”, at Kalyani Government Engineering College from 7-8 April, 2023, organized by IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC and with technical partnership from IETE Kolkata Chapter and IEEE EDS Kolkata Chapter. 3. Sneha Upadhyay, Trisha Sau, Susmita Mitra, Arpita Bhowmik, Saheli Sarkhel and Soumya Pandit, “Statistical Analysis of a Low Power Analog Current Source”, 3rd IEEE Conference on VLSI Device, Circuit and System (VLSI DCS 2022) to be organized by Meghnad Saha Institute of Technology, Kolkata during 19th -20th January, 2022. 4. Saheli Sarkhel, Riya Rani Dey, Soumyarshi Das, Sweta Sarkar, Toushik Santra and Navjeet Bagga, “A Novel Dual Metal Double Gate Grooved Trench MOS Transistor: Proposal and Investigation”, 2nd International Conference on Frontiers in Computing and Systems (COMSYS-2021) during 29th September to 1st October 2021 organized by Department of Electronics & Communication Engineering and Department of Information Technology North-Eastern Hill University (A Central University), Shillong, Meghalaya, India. 5. Taha Saquib, Saheli Sarkhel and Soumya Pandit, "A 0.6 V 1.6 nA Constant Current Reference with Improved Power Supply Sensitivity", 4th International Conference “2021 Devices for Integrated Circuit (DevIC 2021)”, Kalyani Government Engineering College from May 19-20, 2021, organized by IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC and technically co-sponsored by IEEE EDS Kolkata Chapter. 6. Saheli Sarkhel and Navjeet Bagga, “Analytical Model of a Strain Induced Lateral Channel Workfunction Engineered Surrounding Gate MOSFET”, IEEE Conference on Applied Signal Processing, ASPCON 2020, 7th – 9th October, 2020, Jadavpur University. 7. Rishov Aditya, Saheli Sarkhel and Soumya Pandit, “Comparative Study of Doublet OTA Circuit Topologies Operating in Weak Inversion Mode for Low Power Analog IC Applications”, IEEE EDS conference VLSI DCS 2020 on July, 2020 at Meghnad Saha Institute of Technology, Kolkata. 8. Priyanka Saha, Saheli Sarkhel, Pritha Banerjee, Subir Kumar Sarkar, “3D Modeling based Performance Analysis of Gate Engineered Trigate SON TFET with SiO2/HfO2stacked gate oxide”, 2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, 16-17 March 2018. 9. Saheli Sarkhel, Priyanka Saha, Pritha Banerjee and Subir Kumar Sarkar, " Two dimensional analytical modeling based threshold voltage characteristics of proposed linearly graded work function engineered gate all around SB MOSFET", IEEE International Conference on Computing, Power And Communication Technologies 2018 (GUCON) organized by Galgotias University, Noida on September 28-29, 2018. 10. Priyanka Saha, Saheli Sarkhel, Dinesh Kumar Dash, Suvam Senapati and Subir Kumar Sarkar, "Analytical Modeling and Simulation of Triple Metal Front Gate Stack DG- MOSFET with Graded channel (GC-TMDG MOSFET)", Springer International Conference on Communication Devices and Networking (ICCDN) 2017, Sikkim Manipal Institute of Technology, Sikkim from 3rd to 4th June, 2017. (Best Paper Awarded) 11. Saheli Sarkhel, Priyanka Saha and Subir Kumar Sarkar, "Parasitic Fringe Capacitance Modeling of Work Function Engineered Double Gate TFET", in the 2nd IEEE International Conference “Devices for Integrated Circuits (DevIC 2017)”, Kalyani Government Engineering College from March 23-24, 2017. 12. Navjeet Bagga, Saheli Sarkhel and Subir Kumar Sarkar. “Analytical Model for ID-VD characteristics of a Triple Metal Double Gate TFET.” In IEEE International Conference on Computing, Communication and Automation (ICCCA 2016), 29th-30th April 2016, Noida. 13. Saheli Sarkhel, Navjeet Bagga and Subir Kumar Sarkar. “Analytical Modeling and Simulation of Work-function Engineered Gate Junctionless high-k dielectric Double Gate MOSFET: A Comparative Study.” In Michael Faraday IET International Summit-2015 (MFIIS 2015), An IET International Conference 12th -13th September, 2015, Kolkata. 14. Navjeet Bagga, Saheli Sarkhel and Subir Kumar Sarkar. “Recent Research Trends in Gate Engineered Tunnel FET for Improved Current Behaviour by subduing the Ambipolar Effects: A Review.” In IEEE International Conference on Computing, Communication and Automation (ICCCA2015) 15th -16th May 2015, Noida. 15. Saheli Sarkhel, Bibhas Manna and Subir Kumar Sarkar. “A Compact Capacitive Approach based Threshold Voltage Modeling and Performance Comparison of a novel UBR MOSFET with SOI MOSFET.” In 2nd International Conference on Devices, Circuits and Systems (ICDCS 2014), IEEE Conference, 6-8 March, 2014, Coimbatore. 16. Kousik Naskar, Anindya Jana, Saheli Sarkhel, Bibhas Manna and Subir Kumar Sarkar. “Study of power dissipation and delay of two dimensional SOI-SON based MOSFET inverter.” In 2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy (AICERA/ICMiCR), IEEE Conference, June 4-6, 2013, Kerala. 17. Anindya Jana, Kousik Naskar, Saheli Sarkhel, Bibhas Manna, J.K. Singh and Subir Kumar Sarkar. “Realization of Gate performance of OR gate using hybrid Pass transistor based logic circuit.” In 2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy (AICERA/ICMiCR), IEEE Conference, June 4-6, 2013.Kerala. 18. Saheli Sarkhel, Bibhas Manna, Anindya Jana, Kousik Naskar and Subir Kumar Sarkar. “Analytical Potential Distribution Model of Symmetric Double Gate Underlap MOSFET with Binary Metal Alloy as Gate Electrode for Subdued SCEs.” In 2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy (AICERA/ICMiCR), IEEE Conference, June 2013, Kerala. 19. Deepon Saha, Kousik Naskar, Saheli Sarkhel, Bibhas Manna and Subir Kumar Sarkar. “Device Circuit Co-Design of FD-SON MOSFET using BSIMSOI MOSFET Model.” In 2013 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT 2013), IEEE Conference, 17-19 January,2013, IISc Bangalore. 20. Tiya Dey Malakar, Bibhas Manna, Saheli Sarkhel, Sourav Naskar, P. K. Dutta and Subir Kumar Sarkar. “Small - Signal Parameter Extraction to Study the RF Performance of SOI and SON MOSFET.” In 2012 International Conference on Communications, Devices and Intelligent Systems (CODIS 2012), IEEE Conference, 28-29 December 2012, Jadavpur University, Kolkata. 21. Sounak Naha, Saheli Sarkhel and Subir Kumar Sarkar. “A Two Dimensional Analytical Modeling of Fully Depleted Dual Material Gate SON MOSFET and Evidence for Suppressed SCEs.” In 1st International Conference on Devices, Circuits and Systems (ICDCS 2012), IEEE Conference, March 15-16, 2012, Karunya University, Coimbatore.

1. Co-authored a chapter in the book titled "Low-Dimensional Nanoelectronic Devices: Theoretical Analysis and Cutting-Edge Research", CRC Press, Taylor and Francis, October 2022. 2. Co-authored a chapter in the book titled "Nanoelectronics -: Physics, Materials and Devices", Elsevier, January 2023.

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